As the semiconductor industry struggles against the limits of “Moore’s Law”, and dimensional scaling no longer delivers lower gate delay, new solutions are being developed to reduce chip size and lower production costs, while improving reliability, performance and multi-function integration. One emerging method of achieving these aims is 3D-IC where two or more die, potentially for different functions, are stacked and connected in the vertical direction with through-silicon vias (TSV) filled with metal.
Stacking multiple die in a package that meets industry expectations of cost, size and yield presents major challenges. But after many years in development, packages made with TSVs are beginning to appear in commercial applications.
Advanced Packaging Processes: