Through-silicon via (TSV) technology is currently being implemented across a broad range of device types. TSV has the potential to reduce form-factors, increases performance and enable heterogeneous integration.
TSV etching, at depths typically in the 50-200µm range, requires the use of the Bosch process for best control over the wall profile and mask selectivity. Also critical is the via reveal process that exposes the TSV nodes for the subsequent redistribution layer (RDL) metallisation. To perform via reveal, the user grinds the wafer from the backside to a point some 10 to 15µm above the tips of the buried TSV’s. The same Si surface is then dry etched to expose the via tips and leave them proud of the Si surface by approximately 5µm – the “via reveal”.
Benefits of SPTS DRIE for Advanced Packaging
- Broadest range of TSV types from tapered, interposer to via middle & via last
- Controlled scalloping to facilliate subsequent PECVD
- Best in class via reveal process with dual source module
- 2x etch rate compared to competing systems
- Improvement in uniformity
- Complementary oxide etches in the same hardware - reduced cost and footprint
- ReVia® - the industry’s only end-point detection system for via reveal applications for consistent via reveal endpointing regardless of incoming wafer thickness
- ESC design that allows wafer-less plasma cleans for best process stability and clamping through carriers such as glass - improves uptime and eliminates need for wafer back coating
|TSV wafer after Via Reveal
|| "Scallop-free" TSV