eWLB manufacturing leader selects SPTS as their partner for their 300mm ramp
NEWPORT, Wales, June 29, 2010—SPP Process Technology Systems (SPTS), a supplier of advanced capital equipment and process technologies for the global semiconductor industry and related markets, today announced that it has shipped a 300mm Sigma® fxPTM PVD system and a 300mm RVP300 furnace to STATS ChipPAC, a leading service provider of semiconductor packaging design, bump, probe, assembly, test and distribution solutions.
The Sigma® fxPTM system and RVP300 furnace are being used for embedded Wafer-Level Ball Grid Array (eWLB) processing, a ‘fan-out’ Wafer-Level Packaging (WLP) solution. STATS ChipPAC announced the introduction of 300mm eWLB technology on 13th April 2010 . eWLB substrates consist of silicon chips embedded in a mold compound that is sensitive to temperature and susceptible to wafer bow. SPTS’ Sigma® 300mm thin wafer handling system, combined with a novel wafer degas technology specially designed for eWLB, will enable STATS ChipPAC to keep temperature and bow under control without impacting throughput or compromising device electrical performance, while the RVP300 will increase productivity and provide better temperature control than conventional ovens.
“ This is an important design win for SPTS”, said Kevin T. Crofton, Executive Vice President of SPTS. “ We have already proven capability to STATS ChipPAC at 200mm and being selected to join them in their move to 300mm eWLB is an indication of the trust and confidence STATS ChipPAC has in our company and its products.”
“ The Sigma® fxPTM solution used in our 200mm eWLB production is a reliable system,” said Lew Hon Sang, Managing Director of STATS ChipPAC’s facilities in Singapore and Malaysia. “ The eWLB manufacturing process presented unique challenges which we were able to successfully address and establish a robust process that is now in high volume production. With the Sigma® fxP and RVP300 solutions and versatility, STATS ChipPAC also has a broad range of options available to use in the ongoing development of the eWLB technology.”
According to Jerome Baron and Jean-Marc Yannou from market research company Yole Développement, “ Fan-Out WLP is extending the general concept of Wafer Scale Packaging to new application categories, especially the ones with higher pin-counts and larger chip size such as wireless communication ICs. The availability of a 300mm infrastructure for eWLB is excellent news for the IC packaging industry as it will enable FO-WLP packaging technology to become even more cost competitive compared to standard wire-bond and flip-chip BGA technology. Yole expects the overall WLP market growth to top the IC package unit growth this year, with more than 9 Billion units to be shipped, and an impressive CAGR of more than 20% for the next 5 years.”