SPTS IN THE NEWS ARCHIVE

Chip Scale Review: 3D Backside Processing

Comparison between wet and dry silicon via reveal in 3D backside processing

By Dave Thomas, Janet Hopkins, Huma Ashraf, Jash Patel, Oliver Ansell [SPTS Technologies] and Anne Jourdain, Joeri De Vos, Andy Miller, Eric Beyne [imec]

(Originally distributed at the International Wafer-Level Packaging Conference, San Jose, CA Oct. 13-15, 2015)

Wafer backside processing is critical for 3D-IC wafer stacking. Through-silicon vias (TSVs) typically formed using viamiddle processing, are usually exposed from the backside of 300mm device wafers by the combination of mechanical grinding and wet or dry etch processes. A fast via reveal etch is required to have a productive etch rate, but also to have the precision necessary to control within wafer uniformity, selectivity to thin TSV liners and smoothness of postetch surfaces. This makes in situ end-point detection essential for controlled processing, especially as the target tip height is reduced to minimize cost. This paper compares imec’s current wet chemical process of record with SPTS’s dry etch approach. With the dry technique, 1μm nail heights can be controlled within 300nm in order to minimize the overall cost per wafer by eliminating the need for rework steps. The applicability of such a process to extreme wafer thinning to 5μm final Si thickness is also demonstrated

Read the full article at: http://fbs.advantageinc.com/chipscale/may-jun_2016/#47/z

 

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