SPTS IN THE NEWS ARCHIVE

Solid State Technology Magazine, "Advances in Back-Side etching of SiC for GaN"

Article first published by Solid State Technologies in December 2013. Read the full article at: http://electroiq.com/blog/2014/01/advances-in-back-side-via-etching-of-sic-for-gan/

 

ANTHONY BARKER, KEVIN RIDDELL, HUMA ASHRAF and DAVE THOMAS, SPTS Technologies, Newport, UK. CHIA-HAO CHEN, YI-FENG WEI, I-TE CHO and WALTER WOHLMUTH, WIN Semiconductors Corp, Hwaya Technology Park, Taiwan.

The development of an 85µm diameter, 100µm deep SiC back-side via etch process for production is described.

The high breakdown voltage and high electron mobility of GaN make it an attractive material for high power device applications [1]. GaN is typically grown on SiC substrate wafers. Therefore the implementation of back-side vias involves the deep etching of SiC to form conducting pathways to the front-side circuitry [2,3].

Compared to GaAs the material properties of SiC and GaN make them much more challenging to plasma etch. Energetic plasma processes are required to deliver productive SiC etch rates whilst maintaining high enough selectivity to the masking layer and low enough wafer temperature to preserve the bonding and prevent de-lamination. This requires metal masks and careful attention to the method of wafer clamping and temperature control. Due to the ground finish of the pre-etched SiC surface descum break-through steps are essential in minimising defects within the vias to maximise device yields. In such an energetic plasma environment it is challenging to maintain smooth enough SiC walls for subsequent seed metal deposition/electro-plating and to preserve selectivity to the GaN. The build up of relatively low volatility etch by-products within the via and upon the surfaces of the plasma reactor requires effective wet cleans to be developed for both the wafer and the reactor.


Read the full article at: http://electroiq.com/blog/2014/01/advances-in-back-side-via-etching-of-sic-for-gan/

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