Solid State Technology: Fan-Out Wafer Level Packaging: Breakthrough advantages and surmountable challenges

New wafer processing technologies overcome FOWLP’s technical hurdles, paving the way for a new generation of ultra compact, high I/O electronic devices.

BY DAVID BUTLER, SPTS Technologies, an Orbotech company, Newport, UK

Our ability to create ever-smaller electronic devices that maintain or surpass the performance of their physically larger predecessors – exemplified by today’s wearables, smartphones and tablets – is dictated by many factors that extend well beyond Moore’s Law, from the underlying embedded components to the ways in which they’re packaged together. With regard to the latter, fan-out wafer level packaging (FOWLP) is quickly emerging as the new die and wafer level packaging technique of choice, and is widely antici- pated to underpin the next generation of compact, high performance electronic devices.

Read the full article here: http://electroiq.com/blog/2016/08/fan-out-wafer-level-packaging-breakthrough-advantages-and-surmountable-challenges/

Back  |  Top