Plasma Dicing for Next Generation Ultra Small and Ultra Thin Die (14th Sept 2016)
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This webinar was presented live on Wednesday 14th September 2016. To view the webinar, Click Here
Continuing our webinar series on Advanced Packaging applications we presented a second webinar on Plasma Dicing on Wednesday 14th September 2016, with Amandine Pizzagalli, Technology & Market Analyst at Yole Développement.
Semiconductor manufacturers are continually challenged to meet the cost and performance requirements of shrinking devices, and the semiconductor supply chain must collaborate, innovate and evolve in order to keep the industry propelling forward. The demand for thinner wafer and smaller devices has increased over recent years mainly driven by consumer applications such as smartphones, smart cards and stacked packages.
However, thin wafers are creating new challenges of significant interest in the dicing equipment industry. Today, the most common dicing technology applied across memory, logic, MEMS, RFID and power devices is blade dicing. However, needs for thinner wafers have driven the entrance of alternative dicing technologies such as plasma dicing to reduce die fragility, improve die strength, increase the number of chips per wafer and thus reduce Cost Of Ownership of equipment overall.
Part I: Overview of Dicing Technologies and Market Forecast (Amandine Pizzagalli, Yole Développement)
During this webinar, Yole Développement will give its vision and an overview of the key dicing technologies across MEMS devices, power devices, CMOS image sensors, and RFID devices, highlighting its major findings on the evolution and trends of the dicing technologies :
- Technology evolution analysis
- Expectations for the next few years
Part II: Latest Advances in Plasma Dicing (Richard Barnett, SPTS Technologies)
Over the past few years, SPTS has been working closely with a number of customers and industry partners to advance the adoption of plasma dicing, which is widely recognized as an essential technology to enable the next generation of ultra small and ultra thin devices. We have shown that plasma dicing offers significant benefits for a range of applications such as dicing very small or fragile die, where established mechanical and laser techniques can cause reduced throughput or device damage.
In this webinar SPTS will be presenting the latest data illustrating how processing routes affect die strength, share experiences with different types of tapes and other die features such as solder balls. We will share details of the latest equipment which is now available for plasma dicing wafers up to 300mm (on 400mm tape frames) for full production applications.
||Amandine Pizzagalli, Yole Développement
Amandine is in charge of the equipment and material fields for the Advanced Packaging and Manufacturing team at Yole Développement. She graduated as an engineer in electronics, specializing in semiconductors and nanoelectronic technologies. She previously worked for Air Liquide with an emphasis on CVD and ALD processes for semiconductor applications.
Richard Barnett, SPTS Technologies
Richard Barnett is Etch Products Marketing Manager at SPTS, with over 15 years’ experience in the semiconductor and electronics manufacturing industries. Mr. Barnett graduated from The University of Nottingham with a Bachelor’s degree in Engineering for Materials Engineering and Electronics. He has previously worked for LG Semiconductor, Lucas Aerospace, European Semiconductor Manufacturing, Surface Technology Systems and Pure Wafer. He has published technical articles related to silicon DRIE and delivered multiple presentations on wafer processing technologies.
Who should attend?
This webinar will be of interest to:
- Semiconductor professionals involved in design, fabrication and/or packaging of semiconductor and MEMS devices
- Semiconductor Production Engineers responsible for optimizing yield and quality of semiconductor and MEMS devices
- Semiconductor Design Engineers
- Anyone wanting to learn more about the benefits of Plasma Dicing to improve yield and quality of semiconductor and MEMS devices.