Articles and Interviews

i-Micronews: Q&A with Richard Barnett about SPTS's Plasma Dicing solutions, position in the industry and vision of the market 

Date: 15 December, 2016

Yole Developpement had the opportunity to discuss with Richard Barnett (Etch Product Manager) at SPTS Technology about their products, position in the industry and vision of the market. 

Full Interview: http://www.i-micronews.com/manufacturing/8534-plasma-dicing-die-quality-differentiator.html

Driven by rising demand for thinner wafers and stronger die, dicing technology is evolving. According to Yole Développement in its Thin Wafer Processing & Dicing Equipment Market report, the dicing equipment market reached more than US$100 million in 2015 and will double by 2020-2021.

 

TAP Times: "Plasma Dicing - Benefits and Process Considerations"

Author: Richard Barnett (Etch Product Manager)

Date: September 10, 2016

Full Article: http://www.taptimes.com/ftp/September-2016/#/14

Richard Barnett, Etch Product Manager, SPTS Technologies discusses the Benefits and Considerations of Plasma Dicing. Plasma dicing has gained acceptance within the semiconductor industry as a viable alternative to conventional singulation methods using saw blades or lasers, with significant adoption across a range of applications.  

 

Solid State Technology: "Fan-Out Wafer Level Packaging - breakthrough advantages and surmountable challenges

Author: David Butler (EVP, SPTS Technologies)

Date: August 17, 2016

Full Article: http://electroiq.com/blog/2016/08/fan-out-wafer-level-packaging-breakthrough-advantages-and-surmountable-challenges/

David Butler, EVP and General Manager of SPTS Technologies discusses the breakthrough advantages and surmountable challenges of Fan-Out Wafer level packaging. SPTS's ability to create ever-smaller electronic devices that maintain or surpass the performance of their physically larger predecessors

 

Chip Scale Review: "Comparison between wet and dry silicon via reveal in 3D backside processing"

Authors: Dave Thomas et al. (SPTS Technology) and Anne Jourdain et al. (imec)

Date: June 14, 2016

Full Article: http://fbs.advantageinc.com/chipscale/may-jun_2016/#48/z

This paper compares imec's current wet chemical via reveal process of record, based on the selective TMAH chemistry, with SPTS’s dry etch via reveal, based on an SF plasma. State-of-the-art metrology has been used to image large arrays of revealed TSVs. Data on nail height control and uniformity, liner selectivity and surface roughness are presented and discussed.

 

Solid State Technology: "Advances in Back-Side etching of SiC for GaN"

Authors: Anthony Barker et al. (SPTS Technologies) and Chia-Hao Chen et al. (WIN Semiconductors Corp)

Date: May 16, 2016

Full Article: http://electroiq.com/blog/2014/01/advances-in-back-side-via-etching-of-sic-for-gan/

Compared to GaAs the material properties of SiC and GaN make them much more challenging to plasma etch. Energetic plasma processes are required to deliver productive SiC etch rates whilst maintaining high enough selectivity to the masking layer and low enough wafer temperature to preserve the bonding and prevent de-lamination.

  

i-Micronews: Q&A with David Butler concerning the latest Advanced Packaging trends

Date: April 18, 2016

Yole Developpement had the opportunity to interview David Butler, EVP of SPTS. David has shared his point of view on SPTS' involvement in the Chinese Market, its collaboration locally and also the evolution of its product strategy. 

Full Interview: http://www.i-micronews.com/news/advanced-packaging/7260-spts.html

PVD: Our Sigma® fxP is our biggest selling system into the packaging market. We deposit UBM and RDL for WLCSP applications, and for fan-out. We have ~75% share in the FOWLP market for PVD equipment, and are working with all the leading fan-out production companies.

 

i-Micronews: Fan-Out Wafer Level Packaging platform discussed with SPTS Technologies 

Date: April 29, 2015

Yole Developpement had the opportunity to interview David Butler, EVP of SPTS. David has shared his point of view on Fan-Out Wafer Level Packaging platform with us...

Full Interview: http://www.i-micronews.com/advanced-packaging-news/5440-fan-out-wafer-level-packaging-platform-discussed-with-spts-technologies.html

"In the last 12 months, FOWLP has emerged from a relatively small btopics in the packaging world. It started with eWLB, the Infineon designed platform that was licensed to a few companies at the end of the last decade, notably STATS ChipPAC and NANIUM. Those two companies now lead the FOWLP market"ase to become one of the most active 

 

 

 

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