Technical Papers

Below is a list of technical papers which SPTS has published for various journals & conferences in recent years.

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Technical Papers

  1. "Plasma Dicing: Reducing the cost of singulating thinner, smaller die" O. Ansell (iMAPS MINAPAD 2017)
  2. "Plasma Dicing 300mm Framed Wafers - Analysis of Improvement in Die Strength and Cost Benefits for for Thin Die Singulation" M. Blair (ECTC 2017)

  3. "Characterization of Extreme Si Thinning Process for Wafer-to-Wafer Stacking" Inoue et al (ECTC2016)
  4. "Impact of Backside Processing on C-V Characteristics of TSV Capacitors in 3D stacked IC Process flows" D. Thomas et al; SPTS/imec joint paper (EPTC 2015)
  5. "Improving device yields and throughput using plasma dicing" R. Barnett et al (IWLPC 2015)
  6. "Comparison between wet and dry silicon via reveal in 3D backside processing" D. Thomas et al; SPTS/imec joint paper (IWLPC 2015)
  7. "Singulation by Plasma Etching. Integration Techniques to Enable Low Damage, High Productivity Dicing" R. Barnett et al (ASME InterPACK2015)
  8. Wafer-to-Wafer Metal Sputter Deposition Process Control by Automatic Deposition Rate Adjustment" C. Weng et al (CS Mantech 2015)
  9. "Productivity Challenges in PVD Processing in 300mm Pilot Lines for Power Semiconductors" A Rastogi et al. (ASMC 2015)
  10. "Development of an Optically Transparent Silicon Based Technology Platform for Biological Analysis" N Davies et al (IEEE Sensors, Vol 15 No 3, pp1849-1857, Mar2015)
  11. "Extending Capabilities of Etch and Deposition Technologies for 3D Packaging of MEMS in Volume Production" C Short et al (IWLPC2014)
  12. "Advances in Etch and Deposition Technologies for 2.5 and 3D BEOL Processing" K Buchanan et al (SMTA Pan Pacific Symposium Conference 2014)
  13. "Claritas™ – A unique and robust endpoint technology for silicon DRIE processes with open area down to 0.05%" O. Ansell et al (MEMS2014)
  14. "Considerations and Benefits of Plasma Etch Based Wafer Dicing" R. Barnett et al (EPTC 2013)
  15. "Advances in Back-side Via Etching of SiC for GaN Device Applications" A. Barker et al (CS Mantech 2013)
  16. "Dielectric Stack Engineering for Via-Reveal Passivation" K. Crook et al. (ECTC 2013)
  17. "Low Temperature Dielectric Deposition for Via-Reveal Passivation" K. Crook et al. (EMPC 2013)
  18. "Plasma Etch and Low Temperature PECVD Processes for Via Reveal Applications" D. Thomas et al (ECTC 2012)
  19. "3D Multi-stacking of Thin Dies based on TSV and Micro-inserts Interconnections"  J. Souriau et al. (ECTC 2012)
  20. "Refractive Index Graded Anti-Reflection Coating for Solar Cells Based on Low Cost Reclaimed Silicon" Y. Liu et al. (MNE 2012)
  21. "Advanced Deep Reactive-Ion Etching (DRIE) Technology for Hollow Microneedles for Transdermal Blood Sampling and Drug Delivery" Y. Liu et al. (MNE 2011)
  22. "Yield and Productivity Improvements Through Use of Advanced Dual Plasma Source for TSV Reveal & Wafer Dicing Applications" R. Barnett et al. (EPTC 2011)
  23. "300mm Scaling of Critical Silicon Etches for Image Sensor Wafer-Level Packaging Based on Tessera’s MVP (TSV) Technology" D.Thomas et al. (IMAPS 2011)
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