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  • Online Webinar

Addressing the PVD challenges in High Density FO-WLP

Fan-Out Wafer Level Packaging (FO-WLP) is an established advanced packaging format within mobile and automotive sectors, enabling smaller, reliable packages with better performance in a cost-efficient manner. Now starting to expand into applications such as High Performance Computing (HPC) and Networking which require a higher level of integration with greater I/O density, High Density FO-WLP is competing against relatively expensive 2.5D interposer solutions.

In June 2020, Yole projected Fan-Out revenues to grow from $1,256M in 2019 to an estimated $3,046M by 2025, with the largest growth within the sector being in High Density applications[1].

In High Density Fan-Out (HD FO), increased I/O density requires tighter line/space patterning for the redistribution layers (RDL). PVD is used to deposit Cu seed metal prior to RDL electroplating. With an abundance of organic material on the wafer, managing contamination to maintain PVD metal electrical quality and low contact resistance (Rc) is critical, more so as I/O density is increased, and contact structures reduce in size.

Learn how FO-WLP is evolving and why SPTS is the leading PVD production supplier to this important market. We will explain how SPTS’s Sigma® fxP PVD system has all the necessary features that high volume manufacturers require for these emerging HD FO applications, such as specialized pre-treatment technology designed to manage contamination, maintain low and stable Rc, while delivering high uptime, throughput and yields.

This online event requires registration

Date: Wednesday 21st Oct 2020

Session 1: 08:00 UK / 09:00 EU / 15:00 China and Taiwan / 16:00 Korea  

Register for Session 1

Repeat Session:  09:00 PDT (USA) / 12:00 noon EDT (USA) / 17:00 UK / 18:00 EU  

Register for Repeat Session

Please note that BOTH sessions will be live events, and the same slides will be presented in each session

Topics covered:

  • Market Trends and Drivers
  • Process Flow for HD Fan-Out RDL PVD
  • Technical Challenges
  • Solutions

This webinar will be of interest to:

  • Semiconductor professionals involved in design, fabrication and/or packaging of semiconductor devices
  • Semiconductor Production Engineers responsible for optimizing throughput, yield and quality of semiconductor devices
  • Semiconductor Design Engineers
  • Anyone wanting to learn more about Advanced Packaging trends and Fan-Out WLP.

[1] http://www.yole.fr/iso_album/illus_fan-out_revenueforecast_yole_june2020.jpg

Presenter : Chris Jones, Senior Director of PVD and ECD Product Management

Chris Jones is Senior Director for PVD & ECD Product Management. He is responsible for the SPTS PVD and ECD product line covering all aspects of marketing including product positioning and the provision of support to the worldwide sales team.

After completing his BEng in Mechanical Engineering in 1995 at the University of Bristol, UK, he joined SPTS working in Field Service and then Process Engineering before moving into Product Management in 2004.   Chris has presented widely on SPTS products and is an author of several technical articles.