This Application Brief discusses the back-side metallization process for power device manufacturing, and the features of SPTS’s Sigma® fxp which offer reliable wafer handling, effective degas and pre-clean options, film stress control and higher throughputs.
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This Application Brief describes SPTS etch processes for SiC and GaN-on-Si power devices, using our ICP and Synapse etch modules
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This Application Brief describes the reasons GaN is often selected for 5G applications, and SPTS's back-side SiC via and GaN etch processes used in the manufacturing of GaN-on-SiC RF devices.
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In this Application Brief we give an overview of the benefits of the Synapse module for etching AlN and AlScN for BAW device manufacturing, in terms of high etch rate, sidewall angle and end-point control
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Brief introduction to silicon DRIE (The Bosch Process) and its application within MEMS, Advanced Packaging and Power Device manufacturing.
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Download this datasheet explaining how dry blanket Si etching exhibits better control over the etch rate and uniformity, when compared to wet chemical approaches.
Download this datasheet describing how fan-out wafer-level packaging (FOWLP) technology provides higher integration levels and a greater number of external contacts.
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Download this datasheet describing PVD solutions to deposit Under Bump Metallization (UBM) layers, to enable bump metals to adhere to die electrical pad contacts, or to act as seeds for Cu plated Re-Distribution Layers (RDL).
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Stronger die - more die. High yield plasma dicing solutions based on industry leading Deep Reactive Ion Etch (DRIE) technology for dice-before-grind and dice-after-grind.
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End-point detection (EPD) is essential for many wafer etch applications to ensure processes are carefully controlled and consistent.
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High productivity plasma etch processes with unique end-point detection used for post-TSV steps, to prepare the die for connection to other parts of the device.
BioMEMS is an exciting area of the MEMS market, and SPTS offers a range of wafer processes which enable development and commercial manufacturing of BioMEMS
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Piezoelectric properties of AlN to convert mechanical strain into an electric signal, or vice versa is being exploited in devices such as RF filters and a growing number of MEMS.
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Low temp Plasma Enhanced Chemical Vapor Deposition (PECVD) solutions for depositing uniform and stable SiN and SiO films for MEMS devices at temperatures <200°C.
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MEMS microphones have been growing rapidly in recent years for a variety of applications, primarily mobile devices, but also other products such as hearing aids, Bluetooth headsets, and “digital assistants”.
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Molecular Vapor Deposition (MVD®) is a unique process technology that deposits ultra-thin films by vapor deposition at low temperatures on a broad spectrum of substrates.
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Wafer level packaging (WLP) prior to wafer dicing of MEMS devices can provide protection from particles and dicing slurry, while significantly reducing form factor and reducing the overall die cost.
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HF etching is a dry vapour (plasma-less) etch process to remove sacrificial oxide layers, primarily used to release silicon MEMS structures.
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XeF2 vapour etching is a highly selective isotropic etch for removing sacrificial layers of Si, Mo or Ge to release MEMS miccrostructures.
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SiC is a wide bandgap material used in power applications and GaN-on-SiC RF devices. It is very difficult to etch but SPTS' Synapse etch system can provide etch rates 2-4x faster than conventional ICP etching.
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Download this datasheet illustrating how SPTS's PECVD processes can be used for depositing dielectrics for a number of photonic applications, such as thick doped/undoped films for optical waveguides or anti-reflective coating for VCSELs.
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New applications for VCSELs include proximity sensing for automotives and gesture/face recognition for consumer products and SPTS offers a range of processes for VCSEL manufacturing including ICP etch, PVD, and PECVD.
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Overview of the plasma processing technologies which SPTS offers for a variety of Compound Semiconductor applications such as RF, Power and Opto-electronic device manufacturing.
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Download this datasheet giving an overview of SPTS's etch and deposition processes used to manufacture a range of photonic products such as LEDS, optical waveguides, VCSELs and lasers.
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SPTS worked with SK Hynix to increase productivity of their backside via reveal process used in high bandwidth memory chip manufacturing - Optimizing production yield and reducing cost of ownership
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Download this Case Study illustrating how SPTS's Si DRIE technology is used by imec for manufacturing neural probes for mapping brain activity.
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Illustrates the results of a joint development project between SPTS and University of Swansea to create a process for volume production of silicon microneedles for biomedical applications.
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Discusses the introduction of blanket silicon etching to replace CMP, as part of a joint development project with imec to optimize a manufacturable "TSV-last" route for a multi-wafer stack.
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Describes how SPTS worked with Skyworks to significantly improve Mean Time Before Clean (MTBC) for a SiN etch step, used in the manufacturing of their GaAs RF devices.
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Describes how SPTS worked with Qorvo to enable them to successfully install and qualify multiple tools to satisfy the need for a rapid ramp in production of AlN-based BAW filters.
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SPT’s Advanced Vertical Processor (AVP) has been designed to deposit doped and un-doped polysilicon films >4μm thick without wafer sticking
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SPT's LPCVD SiN process that combines the excellent stress control and process repeatability of a PECVD process together with the benefits of low wet etch rate and low ownership cost of an LPCVD system
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Surface transformation to remove the "scallops", created by silicon DRIE during MEMS manufacturing, can be achieved by annealing the Si wafers at high temperature (~1100°C) in a H2 ambient in SPT's RVP furnace.
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