Media Coverage

Driven by rising demand for thinner wafers and stronger die, dicing technology is evolving. “Reaching more than US$100 million in 2015, the dicing equipment market will double by 2020-2021”, announces Yole Développement (Yole) (Source: Thin Wafer Processing & Dicing Equipment Market report, Yole Développement, May 2016). Yet at the same time thin wafers are creating new challenges of significant interest in the dicing equipment industry such as die breakage, chipping, low die strength, handling issues and dicing damage...

Our ability to create ever-smaller electronic devices that maintain or surpass the performance of their physically larger predecessors – exemplified by today’s wearables, smartphones and tablets – is dictated by many factors that extend well beyond Moore’s Law, from the underlying embedded components to the ways in which they’re packaged together. With regard to the latter, fan-out wafer level packaging (FOWLP) is quickly emerging as the new die and wafer level packaging technique of choice, and is widely antici- pated to underpin the next generation of compact, high performance electronic devices.

Wafer backside processing is critical for 3D-IC wafer stacking. Through-silicon vias (TSVs) typically formed using viamiddle processing, are usually exposed from the backside of 300mm device wafers by the combination of mechanical grinding and wet or dry etch processes. A fast via reveal etch is required to have a productive etch rate, but also to have the precision necessary to control within wafer uniformity, selectivity to thin TSV liners and smoothness of postetch surfaces.   

In June 2014, SPTS co-produced a webinar with Ron Huemoeller of Amkor, titled “2.5D and 3D Packaging at the Tipping Point.” We forecasted that significant product announcements would be made over the next 18 months and we were right; sk Hynix, Samsung and Micron all announced readiness for their 3D stacked memory packages, and at the end of the year, AMD started risk production on a high bandwidth 2.5D interposer package, featuring a graphic chip next to four High Bandwidth Memory (HBM) stacks from sk Hynix. 

ITV REPORT: 1,100 jobs created across Wales on eve of investment summit.  The jobs, based in both North and South Wales, will be in the financial and manufacturing sectors. They were announced today, on the eve of the UK Investment Summit at the Celtic Manor Resort in Newport.

Six companies have announced more than 1,000 new jobs in Wales. In Newport, SPTS Technologies has been awarded a Welsh Government grant towards a three-year research project to develop advanced wafer processing solutions for high growth advanced packaging applications in the manufacture of the latest generation of integrated circuits and micro electro mechanical systems (MEMS). The project will create 30 full-time roles.

The announcement that six companies are bringing 1,100 new jobs to Wales is of course good news for the economy, the businesses concerned, and most importantly, for the people who will take up the posts. Thirty jobs over three years at SPTS in Newport may not sound impressive but it is the types of jobs, and the value of what the company does, that makes the company's expansion significant for the Welsh economy. SPTS has been at the Coldra on the eastern edge of Newport for around 20 years and it has always been ahead of the game.

Insider's Made in Wales Awards 2014: SPTS Technologies wins Green Manufacturer Award. Newport-headquartered SPTS, which makes equipment for the microelectronics industry, has made big savings by going green. One judge said: "They've really embraced it. A fantastic story."

At the recent 2.5/3DIC Forum at SEMI Singapore Dr. Surya Bhattacharya, Director of Industry Development (TSV) at, A*STAR Institute of Microelectronics chaired the day long session looking at the state of TSV technology. SPTS updated attendees on their endpoint controlled “via reveal” etch process.