As the semiconductor industry struggles against the limits of “Moore’s Law”, and dimensional scaling no longer delivers lower gate delay, new solutions are being developed to reduce chip size/height and lower production costs, while improving reliability, performance and multi-function integration.
SPTS Technologies offers a broad range of process technologies being used by leading semiconductor packaging companies for advanced packaging schemes - from High Density Fan-Out Wafer Level Packaging (FOWLP) to the most advanced "3D-IC" packages where two or more die, potentially for different functions, are stacked and connected in the vertical direction with through-silicon vias (TSV) filled with metal.
Leveraging our decades of expertise in silicon etching, SPTS offers the most advanced plasma dicing solutions for dicing before grind (DBG) or dicing after grind (DAG) of wafers up to 300mm in diameter.
Advanced Packaging Processes:
- Si Etch - deep TSV etch and blanket silicon etch for via reveal and wafer thinning/CMP elimination
- Plasma Dicing - low damge singulation of small, thin die
- PVD - deposition of metals for UBM/RDL and TSV seed/barrier layers
- PECVD - deposition of dielectrics for passivation and stress-control layers
- LPCVD/Diffusion - large batch processing for thermal oxide deposition and metal anneals