Advanced Packaging

As the semiconductor industry struggles against the limits of “Moore’s Law”, and dimensional scaling no longer delivers lower gate delay, new solutions are being developed to reduce chip size/height and lower production costs, while improving reliability, performance and multi-function integration.

SPTS process technologies are used in many advanced packaging schemes from rapidly growing Fan-Out Wafer Level Packaging (FOWLP) to the most advanced "3D-IC" packages where two or more die, potentially for different functions, are stacked and connected in the vertical direction with through-silicon vias (TSV) filled with metal.

Leveraging our decades of expertise in silicon etching, SPTS offers the most advanced plasma dicing solutions for dicing before grind (DBG), or dicing after grind (DAG) of wafers up to 300mm in diameter.

Advanced Packaging Processes: