Wafer level packaging (WLP) of MEMS, prior to wafer dicing, can provide protection from particles and dicing slurry, and maintain the required environment for accurate device performance, while significantly reducing form factor and reducing the overall die cost. Two examples of wafer level packaging are silicon capping and thin film encapsulation. For more information, click here...
With the drive for improved performance and smaller form factor, packaging schemes based on wafer bumping rather than traditional wire-bond are becoming the default for new designs. PVD systems are used to deposit UBM layers to enable bump metals to adhere to die electrical pad contacts, or to act as seeds for Cu plated RDL. For more information click here...
Blanket silicon etching is required for a growing number of applications, such as post-grind stress relief, over-hang removal, and through silicon via reveal. SPTS offers 200mm and 300mm compatible processes which offer excellent etch rates and uniformity for high productivity and yields. For more information, click here.....
SPTS participates in key industry exhibitions and conferences throughout the year.
Below is the list of upcoming events. Please click on the event for more information.
SPTS - An Orbotech Company (Corporate Video 2015) from SPTS Technologies on Vimeo.
Continuous Improvement Program Event 2014 from SPTS Technologies on Vimeo.
SPTS is a exhibitor and WiFi sponsor at CS Mantech, in Scottsdale, AZ running from 18 - 21 May 2015.
Click here for more details
SPTS Technologies, an Orbotech company, is a leading manufacturer of etch, deposition and thermal processing equipment for the semiconductor industry.