Papers and Presentations

Below is a list of technical papers and presentations which SPTS has published and/or presented at various technical and industry conferences in recent years.

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Technical Papers

  1. "Characterization of Extreme Si Thinning Process for Wafer-to-Wafer Stacking" Inoue et al (ECTC2016)
  2. "Impact of Backside Processing on C-V Characteristics of TSV Capacitors in 3D stacked IC Process flows" D. Thomas et al; SPTS/imec joint paper (EPTC 2015)
  3. "Improving device yields and throughput using plasma dicing" R. Barnett et al (IWLPC 2015)
  4. "Comparison between wet and dry silicon via reveal in 3D backside processing" D. Thomas et al; SPTS/imec joint paper (IWLPC 2015)
  5. "Singulation by Plasma Etching. Integration Techniques to Enable Low Damage, High Productivity Dicing" R. Barnett et al (ASME InterPACK2015)
  6. Wafer-to-Wafer Metal Sputter Deposition Process Control by Automatic Deposition Rate Adjustment" C. Weng et al (CS Mantech 2015)
  7. "Productivity Challenges in PVD Processing in 300mm Pilot Lines for Power Semiconductors" A Rastogi et al. (ASMC 2015)
  8. "Development of an Optically Transparent Silicon Based Technology Platform for Biological Analysis" N Davies et al (IEEE Sensors, Vol 15 No 3, pp1849-1857, Mar2015)
  9. "Extending Capabilities of Etch and Deposition Technologies for 3D Packaging of MEMS in Volume Production" C Short et al (IWLPC2014)
  10. "Advances in Etch and Deposition Technologies for 2.5 and 3D BEOL Processing" K Buchanan et al (SMTA Pan Pacific Symposium Conference 2014)
  11. "Claritas™ – A unique and robust endpoint technology for silicon DRIE processes with open area down to 0.05%" O. Ansell et al (MEMS2014)
  12. "Considerations and Benefits of Plasma Etch Based Wafer Dicing" R. Barnett et al (EPTC 2013)
  13. "Advances in Back-side Via Etching of SiC for GaN Device Applications" A. Barker et al (CS Mantech 2013)
  14. "Dielectric Stack Engineering for Via-Reveal Passivation" K. Crook et al. (ECTC 2013)
  15. "Low Temperature Dielectric Deposition for Via-Reveal Passivation" K. Crook et al. (EMPC 2013)
  16. "Plasma Etch and Low Temperature PECVD Processes for Via Reveal Applications" D. Thomas et al (ECTC 2012)
  17. "3D Multi-stacking of Thin Dies based on TSV and Micro-inserts Interconnections"  J. Souriau et al. (ECTC 2012)
  18. "Refractive Index Graded Anti-Reflection Coating for Solar Cells Based on Low Cost Reclaimed Silicon" Y. Liu et al. (MNE 2012)
  19. "Advanced Deep Reactive-Ion Etching (DRIE) Technology for Hollow Microneedles for Transdermal Blood Sampling and Drug Delivery" Y. Liu et al. (MNE 2011)
  20. "Yield and Productivity Improvements Through Use of Advanced Dual Plasma Source for TSV Reveal & Wafer Dicing Applications" R. Barnett et al. (EPTC 2011)
  21. "300mm Scaling of Critical Silicon Etches for Image Sensor Wafer-Level Packaging Based on Tessera’s MVP (TSV) Technology" D.Thomas et al. (IMAPS 2011)

Presentations

  1. "How Plasma Dicing is Becoming Mainstream" D Butler (SEMI European 3D Summit 2017)
  2. "Extreme Wafer Thinning to 5μm for Low Cost Via-Last" D. Thomas (SPTS/imec joint paper at 3D-ASIP 2016)
  3. "How Plasma Dicing is Finally Becoming Mainstream" R. Barnett (Be-Flexible 2016)
  4. "High Productivity UBM/RDL Deposition By PVD For FOWLP Applications" C.Jones (IWLPC 2016)
  5. "Plasma Dicing: More Die, Stronger Die" R. Barnett (SEMICON Taiwan 2016)
  6. "Improving AlN & ScAlN Thin Film Technology for Next Generation PiezoMEMS" N. Knight (SEMICON Taiwan 2016)
  7. "Deep Silicon Etching - Increasingly Relevant > 20 years on!" D. Thomas et al (ECS 2016)
  8. "FOWLP Goes Mainstream. PVD Solutions For The Fastest Growing Packaging Format" D. Butler (3D Summit 2016) 
  9. "More Die, Stronger Die. Smaller, Thinner, Packages Drives Die Singulation by Plasma Etch" D. Butler (3D ASIP 2015)
  10. "Impact of Backside Processing on C-V Characteristics of TSV Capacitors in 3D stacked IC Process flows" D. Thomas et al; SPTS/imec joint paper (EPTC 2015)
  11. "Improving device yields and throughput using plasma dicing" R. Barnett et al (IWLPC 2015)
  12. "Comparison between wet and dry silicon via reveal in 3D backside processing" D. Thomas et al; SPTS/imec joint presentation (IWLPC 2015)
  13. "Aluminium Nitride Piezoelectric Technology for Next Generation MEMS" D Butler (MEMS Manufacturing 2015)
  14. "High Density Packaging on Wafer Level Fan-out: Deposition and Via Drilling Solutions Tailored for Non-Silicon Substrates" D Butler (SEMI European 3D-TSV Summit, Grenoble, Jan 2015)
  15. "‘Evolution or Revolution? Process Solutions for Next Generation MEMS’" D. Thomas (SEMI MEMS Technical Seminar, Milan Sept 2014)
  16. "Advanced Packaging" K. Buchanan (SEMICON Russia 2014; Advanced Packaging Session 2014)
  17. "PECVD Below 200 Degrees C: Emerging Applications in MEMS" D. Butler (MEMS 2012)
  18. "SPTS Etch Update Prepared for CS Mantech" D. Thomas (CS Mantech 2012)

White Papers

  1. "Panel Fan-Out and Embedded Die" Hanoch Kopel (2016)
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